BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 5)

CONTENTS
Slave Controller – IP Core for Altera FPGAs III-V
5.2.4 Feature Details tab 39
5.2.5 Process Data Interface tab 41
6 Example Designs 49
6.1 EBV Cyclone III DBC3C40 with Digital I/O 50
6.1.1 Configuration and resource consumption 50
6.1.2 Functionality 50
6.1.3 Implementation 50
6.1.4 SII EEPROM 50
6.1.5 Downloadable configuration file 51
6.2 EBV Cyclone IV DBC4CE55 with NIOS 52
6.2.1 Configuration and resource consumption 52
6.2.2 Functionality 52
6.2.3 Implementation 52
6.2.4 SII EEPROM 53
6.2.5 Downloadable configuration file 53
6.3 Altera Cyclone IV DE2-115 with NIOS and MII 54
6.3.1 Configuration and resource consumption 54
6.3.2 Functionality 54
6.3.3 Implementation 55
6.3.4 SII EEPROM 55
6.3.5 Downloadable configuration file 55
6.4 Altera Cyclone IV DE2-115 with NIOS and RGMII 56
6.4.1 Configuration and resource consumption 56
6.4.2 Functionality 56
6.4.3 Downloadable configuration file 56
7 FPGA Resource Consumption 57
8 IP Core Signals 59
8.1 General Signals 59
8.1.1 Clock source example schematics 60
8.2 SII EEPROM Interface Signals 61
8.3 LED Signals 61
8.4 Distributed Clocks SYNC/LATCH Signals 62
8.5 Physical Layer Interface 63
8.5.1 MII Interface 64
8.5.2 RMII Interface 66
8.5.3 RGMII Interface 67
8.6 PDI Signals 70
8.6.1 General PDI Signals 70
8.6.2 Digital I/O Interface 70
8.6.3 SPI Slave Interface 71
8.6.4 Asynchronous 8/16 Bit µController Interface 71