BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 27)

Overview
Slave Controller – IP Core for Altera FPGAs III-15
1.10 Simulation
A behavioral simulation model of the EtherCAT IP core is not available because of its size and
complexity. Thus, simulation of the entire EtherCAT IP Core is not supported, and the EDA Netlist
Writer cannot be used for designs which contain the EtherCAT IP Core. In most cases, simulation of
the EtherCAT IP Core is not necessary, as the IP Core was thoroughly tested and the interfaces are
standardized (Ethernet, Avalon) or simple and well described. Problems at the interface level can
often be solved with a scope shot of the interface signals.
Nevertheless, customer designs using the Avalon or AXI on-chip bus can easily be simulated using a
Bus Functional Model of the on-chip bus slave interface instead of a simulation model of the entire
EtherCAT IP Core.
From th e processor’s view, the EtherCAT IP Core is a memory (or a bunch of registers). For processor
bus verification, the EtherCAT IP Core can be substituted by another IP core with Avalon/AXI slave
interface which behaves like a memory as well. The EtherCAT IP Core can be replaced for simulation
by e.g.:

Altera On-Chip Memory slave

Avalon/AXI slave created with the Qsys