9 timing specification, Timing specification – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual

Page 121

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PDI Description

Slave Controller

– IP Core for Altera FPGAs

III-109

10.3.9 Timing Specification

Table 56: µController timing characteristics IP Core

Parameter

Min

Max

Comment

PRELIMINARY TIMING

t

CS_to_BUSY

x

8

BUSY driven and valid after CS assertion

t

ADR_BHE_setup

x

8

ADR and BHE valid before RD assertion

t

RD_to_DATA_driven

0 ns

9

DATA bus driven after RD assertion

t

RD_to_BUSY

0 ns

9

x

8

BUSY asserted after RD assertion

t

read

External read time (RD assertion to BUSY
deassertion) with normal read busy output
(0x0152[0]). Additional 20 ns if delayed read
busy output is configured.

a) t

read_int

9

a) without preceding write access or
t

WR_to_RD

t

write_int

or configuration: write after

falling edge of WR

b) t

read_int

+ t

write_int

-t

WR_to_RD

9



b) with preceding write access and
t

WR_to_RD

< t

write_int

c) 245 ns

9

c) 8 bit access, absolute worst case with
preceding write access (t

WR_to_RD

=min

,

t

write_int

=max)

d) 285 ns

9

d) 16 bit access, absolute worst case with
preceding write access (t

WR_to_RD

=min

,

t

write_int

=max)

t

read_int


a) 110 ns

9

b) 150 ns

9


a) 150 ns

9

b) 190 ns

9

Internal read time
a) 8 bit access
b) 16 bit access

t

BUSY_to_DATA_valid



a) x

8

-5 ns

b) x

8

-20 ns

DATA bus valid after device BUSY is
deasserted
a) normal read busy output
b) delayed read busy output

t

ADR_BHE_to_DATA_invalid

0 ns

9

DATA invalid after ADR or BHE change

t

CS_RD_to_DATA_release

0 ns

9

x

8

DATA bus released after CS deassertion or
RD deassertion

t

CS_to_BUSY_release

0 ns

9

x

8

BUSY released after CS deassertion

t

CS_delay

0 ns

9

Delay between CS deassertion an assertion

t

RD_delay

x

8

Delay between RD deassertion and
assertion

t

ADR_BHE_DATA_setup

x

8

ADR, BHE and Write DATA valid before WR
deassertion

t

ADR_BHE_DATA_hold

x

8

ADR, BHE and Write DATA valid after WR
deassertion

t

WR_active

x

8

WR assertion time

8

EtherCAT IP Core: time depends on synthesis results

9

EtherCAT IP Core: time depends on synthesis results, specified value has to be met anyway

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