BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 20)

Overview
III-8 Slave Controller – IP Core for Altera FPGAs
Version Release notes
3.0.2
(5/2013) Enhancements:

MI link detection: relaxed checking of PHY register 9 (1000Base-T Master-Slave
Control register)
Restrictions of previous versions which are removed in this version:

EEPROM Emulation is available

General purpose output byte 7 is available
Restrictions of this version, which are removed in V3.0.5:

The AXI PDI may occasionally write incorrect data if simultaneous read and write
accesses occur repeatedly.

RX FIFO size is not initialized by SII EEPROM
Restrictions of this version, which are removed in V3.0.6:

The ERR LED does not allow overriding using the ERR LED Override register
0x0139 while AL Status register Error Indication bit 0x0130[4] is set.
Restrictions of this version, which are removed in V3.0.9:

The AXI PDI may not complete an access occasionally if overlapping read and
write accesses occur, causing the processor to wait endlessly.

The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than
the AXI bus width.
Restrictions of this version, which are removed in V3.0.10:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The AXI PDI may write additional bytes to byte lanes without byte enable, if User
RAM (0x0F80:0x0FFF) or Process Data RAM (0x01000 ff.) is written, if the actual
write address on the bus is 32 bit aligned (AWADDR[1:0]=00), and if one or more
of the lower byte enables/byte strobes (WSTRB) is not set.