BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 139)

Synthesis Constraints
Slave Controller – IP Core for Altera FPGAs III-127
Example Design Constraints File (SDC)
## Constraints for EL9800_DIGI_EP3C25
#
set_time_format -unit ns -decimal_places 3
# Clocks defintion:
create_clock -period 40 -name MII_RX_CLK [get_ports MII_RX_CLK* ]
create_clock -period 40 -name REF_CLK [get_ports REF_CLK ]
create_clock -period 80 -name DIGI_CLK [get_pins
{ETHERCAT_INST|EtherCAT_IPCore_inst|\PDI_DIGI_INST:PDI_INST|NRESET_PDI_SELECT_REG|q}]
derive_pll_clocks
derive_clock_uncertainty
# constraining MII ports
set_input_delay -clock { MII_RX_CLK } 20 [get_ports MII_RX_DATA*]
set_input_delay -clock { MII_RX_CLK } 20 [get_ports MII_RX_DV*]
set_input_delay -clock { MII_RX_CLK } 20 [get_ports MII_RX_ERR*]
set_input_delay -clock { PLL_INST|altpll_component|auto_generated|pll1|clk[0] } 5 [get_ports
nMII_LINK* ]
set_input_delay -clock { PLL_INST|altpll_component|auto_generated|pll1|clk[1] } 5 [get_ports
MII_TX_CLK*]
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_ports {MII_TX_ENA* MII_TX_DATA*}] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_ports {MII_TX_ENA* MII_TX_DATA*}] 8
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {LINK_ACT*}] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {LINK_ACT*}] 15
set_false_path -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_clocks {MII_RX_CLK}]
set_false_path -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_clocks {MII_RX_CLK}]
set_false_path -from [get_clocks {MII_RX_CLK}] -to [get_clocks
{PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {MII_RX_CLK}] -to [get_clocks
{PLL_INST|altpll_component|auto_generated|pll1|clk[1]}]
# constraining logical inputs
set_input_delay -clock { PLL_INST|altpll_component|auto_generated|pll1|clk[0] } 5 [get_ports
{PORT_A* PORT_B* PORT_F*} ]
set_input_delay -clock { PLL_INST|altpll_component|auto_generated|pll1|clk[0] } 5 [get_ports
{PROM_DATA PROM_SIZE}]
set_input_delay -clock { PLL_INST|altpll_component|auto_generated|pll1|clk[0] } 5 [get_ports
MDIO* ]
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_ports {PORT_C* PORT_D* PORT_E*}] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_ports {PORT_C* PORT_D* PORT_E*}] 8
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {PROM_CLK PROM_DATA}] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {PROM_CLK PROM_DATA}] 15
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {MDIO MCLK}] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports {MDIO MCLK}] 15
set_min_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports LED_RUN] 0
set_max_delay -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_ports LED_RUN] 15
#false paths
set_false_path -from {nRESET} -to
{PLL:PLL_INST|altpll:altpll_component|altpll_bbc1:auto_generated|pll_lock_sync}
set_false_path -from
{PLL:PLL_INST|altpll:altpll_component|altpll_bbc1:auto_generated|pll_lock_sync} -to
[get_ports {PROM_DATA PROM_CLK}]
set_false_path -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}] -to
[get_clocks {DIGI_CLK}]
set_false_path -from [get_clocks {PLL_INST|altpll_component|auto_generated|pll1|clk[1]}] -to
[get_clocks {DIGI_CLK}]