BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 26)

Overview
III-14 Slave Controller – IP Core for Altera FPGAs
1.9 OpenCore Plus Evaluation
The EtherCAT IP Core for Altera FPGAs supports OpenCore Plus evaluation. A special License File
with OpenCore Plus support is issued for each user, together with the IP Core Vendor ID package. For
further information on OpenCore Plus, refer
to the Altera Application Note 320 “OpenCore Plus
Evaluation of Megafunctions”, available from Altera ( http://www.altera.com ).
A design with an OpenCore Plus EtherCAT IP Core is subject to some restrictions:

Only a time limited programming file (<design_name>_time_limited.sof) for the Altera Quartus II
Programmer is generated. Other programming files (e.g., .rbf, .pof) are not generated.

For hardware testing, the ESC design has to be connected to the PC running the Altera Quartus II
Programmer using a programming adapter with a JTAG connection. The EtherCAT IP Core is fully
functional while the adapter is connected.

If the connection is interrupted, the EtherCAT IP Core will discontinue its function after
approximately 1 hour.

The OpenCore Plus version slightly increases the resource consumption of the IP Core.

The OpenCore Plus programming file must not be distributed/sold.
A vendor ID package is required for both evaluation and full license. It is recommended to use an
evaluation vendor ID (package) for evaluation, and the original vendor ID for production. The
evaluation vendor ID is beginning with “0xE.......” and ends with the original vendor ID digits.
Evaluation vendor IDs cannot pass the EtherCAT conformance tests.
OpenCore Plus Issues
Sometimes additional top-level pins appear in the OpenCore Plus design, these signals should be
grounded externally if possible. This is a Quartus OpenCore Plus integration issue, not an EtherCAT
IP Core issue. The signals will not appear if a full license is used. Additionally, do not use incremental
synthesis together with OpenCore Plus, since this was found to produce defective designs similar to
the OpenCore Plus integration issue.
Sometimes timing requirements are not met with OpenCore Plus. Experience shows that timing
violations related to the clock altera_reserved_tck can be ignored.
Upgrading to a Full License
A design using an OpenCore Plus EtherCAT IP Core does not have to be changed when upgrading to
a full license, only the full License File has to be installed instead of the OpenCore Plus License File. A
re-generation of the EtherCAT IP Core (running through the MegaWizard) and a new synthesis run is
necessary to generate the unlimited programming files.