BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 67)

Example Designs
Slave Controller – IP Core for Altera FPGAs III-55
6.3.3 Implementation
The SOPC needs to be generated before implementing the example design. Perform the following
steps for implementation:
1. Open Altera Quartus II
2. Open example design from <IPInst_dir>\example_designs\DE2_115_NIOS
3. Choose Tools on the menu bar and select Qsys
…
4. Open Qsys system “DE2_115_EtherCAT_NIOS_QSYS.qsys” and view IP configurations
5. Select Generate on the Generation tab to generate system
6.
Choose “NIOS II” on the menu bar and select “NIOS II Software Build Tools for Eclipse”
7. Select workspace, e.g. create <IPInst_dir>\example_designs\DE2_115_NIOS\workspace
8. Choose File on the menu bar and select New
– “NIOS II Application and BSP from Template”
9. Select SOPC information file “DE2_115_EtherCAT_NIOS_QSYS.sopcinfo”, project template
“EtherCAT DE2-115” and enter project name “EtherCAT_Demo”
10. Select Finish
11. Choose Project on the menu bar and select
“Build all” to build the software project
 “EtherCAT_Demo.elf” file is generated in the Debug-Folder of your workspace directory
12. Select “Make Targets – Build…” from the context menu of the “EtherCAT_Demo” project.
13. Select “mem_init_ generate” and press “Build” button. This will generate the memory initialization
files which will be added to the project later.
14. Switch over to Quartus II window
15.
Select menu “Project – Add/Remove Files in Project…” and add file
“<IPInst_dir>\example_designs\DE2_115_NIOS\software\EtherCAT_Demo\mem_init\meminit.qip”
to project
16. Start compilation (Menu Processing – Start compilation)
17. Download bitstream into FPGA
6.3.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1810 (Altera)/
ET1810 IP Core NIOSII (HW: DE2-115)
6.3.5 Downloadable configuration file
An already synthesized time limited OpenCore Plus configuration file
DE2_115_EtherCAT_NIOS_time_limited.sof
based on this digital I/O example design can be found in the
<IPInst_dir>\example_designs\DE2_115_NIOS\
folder. After expiration of about 1 hour the design quits its operation unless the JTAG connection to
Quartus remains active. This file must only be used for evaluation purposes, any distribution is not
allowed.