BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 63)

Example Designs
Slave Controller – IP Core for Altera FPGAs III-51
6.1.5 Downloadable configuration file
An already synthesized time limited OpenCore Plus configuration file
DBC3C40_EtherCAT_DIGI_time_limited.sof
based on this digital I/O example design can be found in the
<IPInst_dir>\example_designs\DBC3C40_EtherCAT_DIGI\
folder. After expiration of about 1 hour the design quits its operation unless the JTAG connection to
Quartus remains active. This file must only be used for evaluation purposes, any distribution is not
allowed.