BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 93)

Ethernet Interface
Slave Controller – IP Core for Altera FPGAs III-81
9.3 RMII Interface
The IP Core supports RMII with 2 communication ports. Nevertheless, MII is recommended since the
PHY delay (and delay jitter) is smaller in comparison to RMII.
The Beckhoff ESCs have additional requirements to Ethernet PHYs using RMII, which are easily
accomplished by several PHY vendors.
Refer to “Section I – Technology” for Ethernet PHY requirements.
Additional information regarding the IP Core:

The clock source of the PHYs is the same as for the FPGA (25 MHz quartz oscillator)

The signal polarity of nRMII_LINK is not configurable inside the IP Core, nRMII_LINK is active low.
If necessary, the signal polarity must be swapped outside the IP Core.

The IP Core can be configured to use the MII management interface for link detection and link
configuration.

The IP Core supports arbitrary PHY addresses.
For details about the ESC RMII Interface refer to Section I.
9.3.1 RMII Interface Signals
The RMII interface of the IP Core has the following signals:
EtherCAT
device
nRMII_LINK
CLK50
RMII_RX_DV
RMII_RX_ERR
RMII_RX_DATA[1:0]
RMII_TX_ENA
RMII_TX_DATA[1:0]
NPHY_RESET_OUT
Figure 29: RMII Interface signals