BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 131)

PDI Description
Slave Controller – IP Core for Altera FPGAs III-119
10.5.2 Configuration
The AXI3 interface has PDI type 0x80 in the PDI control register 0x0140 and on-chip bus subtype
“000” in the PDI on-chip bus extended configuration register 0x0152:0x0153. The AXI clock speed and
the AXI data bus width are configurable in the AXI PDI configuration dialog.
Device emulation
Enable Device emulation (0x0141[0]=1). This feature should be disabled in most use cases, since the
processor will hande the EtherCAT state machine.
On-chip Bus CLK
The AXI bus clock period can be selected from a wide range. Nevertheless, configuring the bus clock
to be a multiple of 25 MHz will result in best performance:
AXI bus clock frequency = N * 25 MHz (N=1...31)
The maximum clock speed depends on the FPGA and the synthesis. The rising edge of AXI clock has
to be synchronous with the rising edge of CLK25 of the EtherCAT IP Core (otherwise the bus clock is
asynchronous).
On-chip Bus CLK is asynchronous to CLK25 core clock
Select this option if the bus clock is asynchronous and synchronization is required (results in extra
delay).
External data bus width
Select the AXI data bus width (PDI_EXT_BUS_WIDTH=8/16/32/64 bit). A higher data bus width
results in higher performance, since the individual bytes are prefetched internally.
ID width
Select the AXI data bus ID signal width
10.5.3 Interrupts
The AXI Slave interface supports up to 3 interrupts for easy connection to embedded systems:

the global PDI interrupt (IRQ_MAIN)

The DC SyncSignals can be used as interrupts by means of the Qsys IRQ bridge.