BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 126)

PDI Description
III-114 Slave Controller – IP Core for Altera FPGAs
10.4.2 Configuration
The Avalon interface has PDI type 0x80 in the PDI control register 0x0140. The Avalon clock speed
and the Avalon data bus width are configurable in the Avalon PDI configuration dialog.
Device emulation
Enable Device emulation (0x0141[0]=1). This feature should be disabled in most use cases, since the
processor will hande the EtherCAT state machine.
On-chip Bus CLK
The Avalon bus clock period can be selected from a wide range. Nevertheless, configuring the bus
clock to be a multiple of 25 MHz will result in best performance:
Avalon bus clock frequency = N * 25 MHz (N=1...31)
The maximum clock speed depends on the FPGA and the synthesis. The rising edge of Avalon clock
has to be synchronous with the rising edge of CLK25 of the EtherCAT IP Core (otherwise the bus
clock is asynchronous).
On-chip Bus CLK is asynchronous to CLK25 core clock
Select this option if the bus clock is asynchronous and synchronization is required (results in extra
delay).
External data bus width
Select the Avalon data bus width (PDI_EXT_BUS_WIDTH=8/16/32/64 bit). A higher data bus width
results in higher performance, since the individual bytes are prefetched internally.
10.4.3 Interrupts
The Avalon Slave interface supports up to 3 interrupts for easy connection in the Altera SOPC Builder:

the global PDI interrupt (IRQ)

DC SYNC0 and DC SYNC1. These interrupts are available if DC are selected. The DC
SyncSignals are also available as standard DC Sync0/1 signals.
10.4.4 Data Bus With and SyncManager Configuration
Since an Avalon master always performs read accesses with the whole data bus width (e.g. 32 bit for
a NIOS II processor) regardless of the actually issued read command (8/16/32 bit) without use of byte
enable signals, care has to be taken especially for SyncManager configuration. SyncManagers should
be configured with a length and alignment of multiples of this data width. For write accesses, byte
enable signals are used to identify bytes which have to be written.