BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 8)

TABLES
III-VIII Slave Controller – IP Core for Altera FPGAs
TABLES
Table 1: IP Core Main Features .............................................................................................................. 1
Table 2: Frame Processing Order ........................................................................................................... 2
Table 3: Tested FPGA/Designflow combinations .................................................................................... 5
Table 4: Release notes ............................................................................................................................ 6
Table 5: Register Revision (0x0001) ..................................................................................................... 12
Table 6: Register Build (0x0002:0x0003) .............................................................................................. 12
Table 7: IP Core Feature Details ........................................................................................................... 16
Table 8: Legend ..................................................................................................................................... 18
Table 9: Register availability.................................................................................................................. 19
Table 10: Legend ................................................................................................................................... 21
Table 11: Extended ESC Features (Reset values of User RAM – 0x0F80:0x0FFF) ............................ 22
Table 12: Contents of lib folder.............................................................................................................. 27
Table 13: Resource consumption Digital I/O example design DBC3C40 ............................................. 50
Table 14: Resource consumption NIOS example design DBC4CE55 .................................................. 52
Table 15: Resource consumption NIOS example design DE2-115 MII ................................................ 54
Table 16: Resource consumption NIOS example design DE2-115 RGMII ........................................... 56
Table 17: Typical need of Logic Cells (LE) for main configurable functions ......................................... 57
Table 18: EtherCAT IP Core configuration for typical EtherCAT Devices ............................................ 58
Table 19: General Signals ..................................................................................................................... 59
Table 20: SII EEPROM Signals ............................................................................................................. 61
Table 21: LED Signals ........................................................................................................................... 61
Table 22: DC SYNC/LATCH signals ..................................................................................................... 62
Table 23: Physical Layer General ......................................................................................................... 63
Table 24: PHY Interface MII .................................................................................................................. 64
Table 25: PHY Interface RMII................................................................................................................ 66
Table 26: PHY Interface RGMII ............................................................................................................. 67
Table 27: General PDI Signals .............................................................................................................. 70
Table 28: Digital I/O PDI ........................................................................................................................ 70
Table 29: SPI PDI .................................................................................................................................. 71
Table 30: 8/16 Bit µC PDI ...................................................................................................................... 71
Table 31: 8 Bit µC PDI ........................................................................................................................... 71
Table 32: 16 Bit µC PDI ......................................................................................................................... 72
Table 33: Avalon PDI ............................................................................................................................. 72
Table 34: AXI3 PDI ................................................................................................................................ 73
Table 35: PHY management Interface signals ...................................................................................... 74
Table 36: MII management timing characteristics ................................................................................. 75
Table 37: MII Interface signals .............................................................................................................. 77
Table 38: MII TX Timing characteristics ................................................................................................ 79
Table 39: MII timing characteristics ....................................................................................................... 79
Table 40: RMII Interface signals ............................................................................................................ 82
Table 41: RGMII Interface signals ......................................................................................................... 84
Table 42: Available PDIs for EtherCAT IP Core .................................................................................... 87
Table 43: IP core digital I/O signals ....................................................................................................... 88
Table 44: Input/Output byte reference ................................................................................................... 88
Table 45: Digital I/O timing characteristics IP Core ............................................................................... 91
Table 46: SPI signals ............................................................................................................................. 94
Table 47: Address modes ...................................................................................................................... 95
Table 48: SPI commands CMD0 and CMD1 ......................................................................................... 96
Table 49: Interrupt request register transmission .................................................................................. 96
Table 50: Write access for 2 and 4 Byte SPI Masters ........................................................................... 98
Table 51: SPI timing characteristics IP Core ......................................................................................... 99
Table 52: Read/Write timing diagram symbols .................................................................................... 100
Table 53: µController signals ............................................................................................................... 105
Table 54: 8 bit µController interface access types .............................................................................. 106
Table 55: 16 bit µController interface access types ............................................................................ 106
Table 56: µController timing characteristics IP Core ........................................................................... 109
Table 57: Avalon signals ..................................................................................................................... 113
Table 58: Avalon timing characteristics ............................................................................................... 115
Table 59: AXI3 signals ......................................................................................................................... 117
Table 60: AXI timing characteristics .................................................................................................... 120