BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 79)

IP Core Signals
Slave Controller – IP Core for Altera FPGAs III-67
8.5.3 RGMII Interface
Table 26 lists the signals used with RGMII.
Table 26: PHY Interface RGMII
Condition Name Direction Description
Port0 =
RGMII
CLK25_2NS INPUT 25 MHz clock signal from
PLL (rising edge 2 ns after
rising edge of CLK25),
used for RGMII GTX_CLK
nRGMII_LINK0 INPUT 0: 100 Mbit/s (Full
Duplex) link at port 0
1: no link at port 0
RGMII_RX_CLK0 INPUT Receive clock port 0
RGMII_RX_CTL_DATA_DDR_CLK0
OUTPUT
Receive control/data DDR
input clock port 0
RGMII_RX_CTL_DATA_DDR_NRESET0
OUTPUT
Receive control/data DDR
input reset (act. Low) port 0
RGMII_RX_CTL_DDR_L0 INPUT Receive control DDR input
low port 0
RGMII_RX_CTL_DDR_H0 INPUT Receive control DDR input
high port 0
RGMII_RX_DATA_DDR_L0 INPUT Receive data DDR input
low port 0
RGMII_RX_DATA_DDR_H0 INPUT Receive data DDR input
high port 0
RGMII_TX_CLK_DDR_CLK0 OUTPUT Transmit clock DDR output
clock port 0
RGMII_TX_CLK_DDR_NRESET0 OUTPUT Transmit clock DDR output
reset (port 0, act. Low)
RGMII_TX_CLK_DDR_L0 OUTPUT Transmit clock DDR output
low port 0
RGMII_TX_CLK_DDR_H0 OUTPUT Transmit clock DDR output
high port 0
RGMII_TX_CTL_DATA_DDR_CLK0 OUTPUT Transmit control/data DDR
output clock port 0
RGMII_TX_CTL_DATA_DDR_NRESET0 OUTPUT Transmit control/data DDR
output reset (port 0, act.
Low)
RGMII_TX_CTL_DDR_L0 OUTPUT Transmit control DDR
output low port 0
RGMII_TX_CTL_DDR_H0 OUTPUT Transmit control DDR
output high port 0
RGMII_TX_DATA_DDR_L0 OUTPUT Transmit data DDR output
low port 0