BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 12)

ABBREVIATIONS
III-XII Slave Controller – IP Core for Altera FPGAs
ABBREVIATIONS
µC
Microcontroller
ADR Address
AL Application Layer
AMBA ® Advanced Microcontroller Bus Architecture from ARM ®
AXI TM Advanced eXtensible Interface Bus, an AMBA interconnect. Used as On-Chip-bus
BHE Bus High Enable
CMD Command
CS Chip Select
DC Distributed Clock
DL Data Link Layer
ECAT EtherCAT
ESI EtherCAT Slave Information
EOF End of Frame
ESC EtherCAT Slave Controller
FMMU Fieldbus Memory Management Unit
FPGA Field Programmable Gate Array
GPI General Purpose Input
GPO General Purpose Output
HDL Hardware Description Language
IP Intellectual Property
IRQ Interrupt Request
LC Logic Cell
LE Logic Element
MAC Media Access Controller
MDIO Management Data Input / Output
MI (PHY) Management Interface
MII Media Independent Interface
MISO Master In – Slave Out
MOSI Master Out – Slave In
PDI Process Data Interface
PLD Programmable Logic Device
PLL Phase Locked Loop
RBF Raw Binary File
RD Read
RMII Reduced Media Independent Interface
SM SyncManager
SoC System on a Chip
SOF Start of Frame
SOPC System on a programmable Chip
SPI Serial Peripheral Interface
VHDL Very High Speed Integrated Circuit Hardware Description Language
WR Write