BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 18)

Overview
III-6 Slave Controller – IP Core for Altera FPGAs
1.7 Release Notes
EtherCAT IP Core updates deliver feature enhancements and removed restrictions. Feature
enhancements are not mandatory regarding conformance to the EtherCAT standard. Restrictions
have to be judged whether they are
relevant in the user’s configuration or not, or if workarounds are
possible.
Table 4: Release notes
Version Release notes
3.0.0
(3/2013) 
Update to Quartus II 11.0 with Qsys support

Removed small/medium/large register sets, added updated preset configurations
Enhancements:

Increased PDI performance

Support for 8/16/32/64 bit Avalon and AXI3 TM interface

Support for RGMII ports (added DE2-115 RGMII example design)

Native support for FX PHYs

Support for individual PHY address configuration and reading out this
configuration

Support for static or dynamic PHY address configuration

Support for 0 KB Process RAM, DC Sync/Latch signals individually configurable,
LED test added

Support for PDI SyncManager/IRQ acknowledge by Write command

Device emulation is now configured in the GUI statically.
Restrictions of this version, which are removed in V3.0.1:

Distributed Clocks are not available

AXI PDI is not available

RMII is not available

A time limit of 1 hour for evaluation purposes is enabled even without OpenCore
Plus

The DBC3C40 and DBC4CE55 example designs are occasionally causing the
PHY port 0 to fall into Isolate mode
Restrictions of this version, which are removed in V3.0.2:

EEPROM Emulation is not available

General purpose output byte 7 is not available
Restrictions of this version, which are removed in V3.0.5:

The AXI PDI may occasionally write incorrect data if simultaneous read and write
accesses occur repeatedly.

RX FIFO size is not initialized by SII EEPROM
Restrictions of this version, which are removed in V3.0.6:

The ERR LED does not allow overriding using the ERR LED Override register
0x0139 while AL Status register Error Indication bit 0x0130[4] is set.
Restrictions of this version, which are removed in V3.0.9:

The AXI PDI may not complete an access occasionally if overlapping read and
write accesses occur, causing the processor to wait endlessly.

The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than
the AXI bus width.
Restrictions of this version, which are removed in V3.0.10:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,