FIGURES
III-X
Slave Controller
– IP Core for Altera FPGAs
Figure 1: EtherCAT IP Core Block Diagram ............................................................................................ 1
Figure 2: Frame Processing .................................................................................................................... 2
Figure 3: Design flow ............................................................................................................................. 13
Figure 4: Files installed with EtherCAT IP Core setup .......................................................................... 26
Figure 5: License Setup ......................................................................................................................... 28
Figure 6: Qsys with EtherCAT IP Core .................................................................................................. 31
Figure 7: EtherCAT IP Core Configuration Interface ............................................................................. 32
Figure 8: Documentation ....................................................................................................................... 33
Figure 9: Product ID tab ........................................................................................................................ 34
Figure 10: Physical Layer tab ................................................................................................................ 35
Figure 11: Internal Functions tab ........................................................................................................... 37
Figure 12: Feature Details tab ............................................................................................................... 39
Figure 13: Available PDI Interfaces ....................................................................................................... 41
Figure 14: Register Process Data Interface .......................................................................................... 42
Figure 15: Register PDI
– Digital I/O Configuration............................................................................... 43
Figure 16: Register PDI
– µC-Configuration.......................................................................................... 45
Figure 17: Register PDI
– SPI Configuration ......................................................................................... 46
Figure 18: Register PDI
– Avalon Interface Configuration .................................................................... 47
Figure 19: Register PDI
– AXI3 Interface Configuration ....................................................................... 48
Figure 20: EtherCAT IP Core clock source (MII) ................................................................................... 60
Figure 21: EtherCAT IP Core clock source (RMII) ................................................................................ 60
Figure 22: EtherCAT IP Core clock source (RGMII) ............................................................................. 60
Figure 23: PHY management Interface signals..................................................................................... 74
Figure 24: Example schematic with two individual MII management interfaces ................................... 75
Figure 25: MII Interface signals ............................................................................................................. 77
Figure 26: MII TX Timing Diagram ........................................................................................................ 78
Figure 27: MII timing RX signals............................................................................................................ 79
Figure 28: MII example schematic......................................................................................................... 80
Figure 29: RMII Interface signals........................................................................................................... 81
Figure 30: RMII example schematic ...................................................................................................... 82
Figure 31: RGMII Interface signals ........................................................................................................ 84
Figure 32: RGMII example schematic ................................................................................................... 85
Figure 33: IP core digital I/O signals ..................................................................................................... 88
Figure 34: Digital Output Principle Schematic ....................................................................................... 90
Figure 35: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 92
Figure 36: Digital Input: Input data sampled with LATCH_IN ................................................................ 92
Figure 37: Digital Input: Input data sampled with SYNC0/1 .................................................................. 92
Figure 38: Digital Output timing ............................................................................................................. 93
Figure 39: OUT_ENA timing .................................................................................................................. 93
Figure 40: SPI master and slave interconnection.................................................................................. 94
Figure 41: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .. 100
Figure 42: SPI read access (2 byte addressing, 1 byte read data) with Wait State byte .................... 101
Figure 43: SPI read access (2 byte addressing, 2 byte read data) with Wait State byte .................... 102
Figure 44: SPI write access (2 byte addressing, 1 byte write data) .................................................... 103
Figure 45: SPI write access (3 byte addressing, 1 byte write data) .................................................... 104
Figure 46: µController interconnection ................................................................................................ 105
Figure 47: Connection with 16 bit µControllers without byte addressing ............................................ 107
Figure 48: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open) .......... 108
Figure 49: Read access (without preceding write access) .................................................................. 110
Figure 50: Write access (write after rising edge nWR, without preceding write access) .................... 111
Figure 51: Sequence of two write accesses and a read access ......................................................... 111
Figure 52: Write access (write after falling edge nWR) ....................................................................... 112
Figure 53: Avalon signals .................................................................................................................... 113
Figure 54: Avalon Read Access (W=1) ............................................................................................... 116
Figure 55: Avalon Read Access (D=8 Bit, W=4) ................................................................................. 116
Figure 56: Avalon Write Access (4 accesses) ..................................................................................... 116
Figure 57: AXI3 signals ....................................................................................................................... 117
Figure 58: AXI Read Access ............................................................................................................... 121
Figure 59: AXI Write Access ................................................................................................................ 121
Figure 60: Distributed Clocks signals .................................................................................................. 122
