4 distributed clocks sync/latch signals, Distributed clocks sync/latch signals, Table 22: dc sync/latch signals – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual

4 distributed clocks sync/latch signals, Distributed clocks sync/latch signals, Table 22: dc sync/latch signals | BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual | Page 74 / 141