1 tx_clk delay in phy, 2 tx_clk delay on pcb, 3 tx_clk delay in fpga with pll – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual

Page 98: 4 tx_clk delay in fpga without pll

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1 tx_clk delay in phy, 2 tx_clk delay on pcb, 3 tx_clk delay in fpga with pll | 4 tx_clk delay in fpga without pll | BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual | Page 98 / 141 1 tx_clk delay in phy, 2 tx_clk delay on pcb, 3 tx_clk delay in fpga with pll | 4 tx_clk delay in fpga without pll | BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual | Page 98 / 141
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