Motorola 68P02958C00-B - Manual (Page 312)

Software Diagnostics Output
C-20
18. The number of empty frames ready to be received.
19. The number of frames received.
20. The number of frames transmitted.
21. The number of empty frames directed to transmission.
## 261 LEVEL = 1
HDLC hardware control and status :-
Internal software data (key)
(DATA) : %% 1
Internal hardware registers (IREG) : %% 2
Internal hardware parameters (IRAM) : %% 3
Scc configuration register (SCON) : %% 4
Scc mode register (SCM) : %% 5
Scc data sync. register (DSR) : %% 6
Scc event register (SCCE) : %% 7
Scc mask register (SCCM) : %% 8
Scc status register (SCCS) : %% 9
Temp receive crc (RCRC_L/H) : %% %% 10
Crc polynom mask (C_MASK_L/H) : %% %% 10
Temp transmit crc (TCRC_L/H) : %% %% 10
Discard frame counter (DISFC) : %% 10
Crc error counter (CRCEC) : %% 10
Abort sequence counter (ABTSC) : %% 10
Nonmatch address counter (NMARC) : %% 10
Frame retransmit counter (RETRC) : %% 10
Receive frame maximum length (MFLR) : %% 10
Receive frame length counter (MAX_CNT) : %% 10
User define frame address mask (HMASK) : %% 11
User define frame addresses (HADDRX) : %% %% %% %% 12
1. Device key address.
2. Address of H-W registers.
3. Address of H-W parameters.
4. Determines the clock direction (Rx or Tx) and the baud rate
5. Determines the work mode — HDLC or UART.
6. Determines the HDLC flags.
7. The events that generate the interrupt.
8. Mask to block the interrupt.
9. The CM (Channel Monitor) and TD (Tone Detect) statuses.
10. Not in use.
11. Mask of received addresses.
12. The addresses to which this site responds via this port.