SMSC LAN9312 - Manual (Page 106)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 106 SMSC LAN9312
DATASHEET
8.4.4 PIO Reads
PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can
be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both
nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for
the period specified in
Table 15.8, “PIO Read Cycle Timing Values,” on page 446 . The cycle ends when
either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Read data is valid as indicated in the functional timing diagram in
Figure 8.3 .
The endian select signal (END_SEL) has the same timing characteristics as the address lines.
Please refer to Section 15.5.4, "PIO Read Cycle Timing," on page 446 for the AC timing specifications
for PIO read operations.
Note: Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer
to
Section 8.4.2 for information on these restrictions.
Figure 8.3 Functional Timing for PIO Read Operation
VALID
VALID D[31:0] (OUTPUT)
nCS, nRD
A[x:2]
VALID END_SEL