SMSC LAN9312 - Manual (Page 168)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 168 SMSC LAN9312
DATASHEET
14.2 System Control and Status Registers
The System CSR’s are directly addressable memory mapped registers with a base address offset
range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).
Table 14.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 9 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
„ Section 14.2.1, "Interrupts," on page 172
„ Section 14.2.2, "Host MAC & FIFO’s," on page 180
„ Section 14.2.3, "GPIO/LED," on page 192
„ Section 14.2.4, "EEPROM," on page 197
„ Section 14.2.5, "IEEE 1588," on page 201
„ Section 14.2.6, "Switch Fabric," on page 229
„ Section 14.2.7, "PHY Management Interface (PMI)," on page 243
„ Section 14.2.8, "Virtual PHY," on page 245
„ Section 14.2.9, "Miscellaneous," on page 259
Table 14.1 System Control and Status Registers
ADDRESS
OFFSET SYMBOL REGISTER NAME
050h ID_REV Chip ID and Revision Register, Section 14.2.9.1
054h IRQ_CFG Interrupt Configuration Register, Section 14.2.1.1
058h INT_STS Interrupt Status Register, Section 14.2.1.2
05Ch INT_EN Interrupt Enable Register, Section 14.2.1.3
060h RESERVED Reserved for Future Use
064h BYTE_TEST Byte Order Test Register, Section 14.2.9.2
068h FIFO_INT FIFO Level Interrupts Register, Section 14.2.1.4
06Ch RX_CFG Receive Configuration Register, Section 14.2.2.1
070h TX_CFG Transmit Configuration Register, Section 14.2.2.2
074h HW_CFG Hardware Configuration Register, Section 14.2.9.3
078h RX_DP_CTRL RX Datapath Control Register, Section 14.2.2.3
07Ch RX_FIFO_INF Receive FIFO Information Register, Section 14.2.2.4
080h TX_FIFO_INF Transmit FIFO Information Register, Section 14.2.2.5
084h PMT_CTRL Power Management Control Register, Section 14.2.9.4
088h RESERVED Reserved for Future Use
08Ch GPT_CFG General Purpose Timer Configuration Register,
Section 14.2.9.5
090h GPT_CNT General Purpose Timer Count Register, Section 14.2.9.6
094h - 098h RESERVED Reserved for Future Use