Chapter 6 switch fabric, 1 functional overview, 2 switch fabric csrs – SMSC LAN9312 User Manual

Page 55: Chapter 6, Switch fabric, Functional overview, Switch fabric csrs, Datasheet

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

55

Revision 1.4 (08-19-08)

DATASHEET

Chapter 6 Switch Fabric

6.1

Functional Overview

At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The
switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and
priority tagged frames. The switch fabric provides an extensive feature set which includes spanning
tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by
VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of
prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while
forwarding operations are completed, and a 1K entry forwarding table provides room for MAC address
forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue
size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed
dynamically via the buffer manager block within the switch fabric. All aspects of the switch fabric are
managed via the switch fabric configuration and status registers (CSR), which are indirectly accessible
via the memory mapped system control and status registers.

The switch fabric consists of four major block types:

„

Switch Fabric CSRs

- These registers provide access to various switch fabric parameters for

configuration and monitoring.

„

10/100 Ethernet MACs

- A total of three MACs are included in the switch fabric which provide basic

10/100 Ethernet functionality for each switch fabric port.

„

Switch Engine (SWE)

- This block is the core of the switch fabric and provides VLAN layer 2

switching for all three switch ports.

„

Buffer Manager (BM)

- This block provides control of the free buffer space, transmit queues, and

scheduling.

Refer to

Figure 2.1 Internal LAN9312 Block Diagram on page 21

for details on the interconnection of

the switch fabric blocks within the LAN9312.

6.2

Switch Fabric CSRs

The switch fabric CSRs provide register level access to the various parameters of the switch fabric.
Switch fabric related registers can be classified into two main categories based upon their method of
access: direct and indirect.

The directly accessible switch fabric registers are part of the main system CSRs of the LAN9312 and
are detailed in

Section 14.2.6, "Switch Fabric," on page 229

. These registers provide switch fabric

manual flow control (Ports 0-2), data/command registers (for access to the indirect switch fabric
registers), and switch MAC address configuration.

The indirectly accessible switch fabric registers reside within the switch fabric and must be accessed
indirectly via the

Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)

and

Switch Fabric

CSR Interface Command Register (SWITCH_CSR_CMD)

, or the set of

Switch Fabric CSR Interface

Direct Data Register (SWITCH_CSR_DIRECT_DATA)

. The indirectly accessible switch fabric CSRs

provide full access to the many configurable parameters of the switch engine, buffer manager, and
each switch port. The switch fabric CSRs are detailed in

Section 14.5, "Switch Fabric Control and

Status Registers," on page 307

.

For detailed descriptions of all switch fabric related registers, refer to

Chapter 14, "Register

Descriptions," on page 166

.

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