39 switch engine interrupt mask register (swe_imr), Switch engine interrupt mask register (swe_imr), Switch engine interrupt mask – SMSC LAN9312 User Manual
Page 408: Register (swe_imr), Switch engine, Interrupt mask register (swe_imr), For the, Section 14.5.3.39, Datasheet
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
408
SMSC LAN9312
DATASHEET
14.5.3.39
Switch Engine Interrupt Mask Register (SWE_IMR)
This register contains the Switch Engine interrupt mask, which masks the interrupts in the
Engine Interrupt Pending Register (SWE_IPR)
. All Switch Engine interrupts are masked by setting the
Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to
Chapter 5, "System Interrupts,"
for more information.
Register #:
1880h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:1
RESERVED
RO
-
0
Interrupt Mask
When set, this bit masks interrupts from the Switch Engine. The status bits
in the
Switch Engine Interrupt Pending Register (SWE_IPR)
are not
affected.
R/W
1b