7 free running 25mhz counter register (free_run), Free running 25mhz counter register (free_run), Section 14.2.9.7 – SMSC LAN9312 User Manual
Page 267: Datasheet
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
267
Revision 1.4 (08-19-08)
DATASHEET
14.2.9.7
Free Running 25MHz Counter Register (FREE_RUN)
This read-only register reflects the current value of the free-running 25MHz counter. Refer to
12.2, "Free-Running Clock," on page 161
for additional information.
Offset:
09Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Free Running Counter (FR_CNT)
This field reflects the current value of the free-running 32-bit counter. At
reset, the counter starts at zero and is incremented by one every 25MHz
cycle. When the maximum count has been reached, the counter will rollover
to zero and continue counting.
Note:
The free running counter can take up to 160nS to clear after a reset
event.
RO
00000000h