SMSC LAN9312 - Manual (Page 216)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 216 SMSC LAN9312
DATASHEET
14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)
T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h 1 5 8 8 C l o c k Ta r g e t L o w - D W O R D R e g i s t e r
(1588_CLOCK_TARGET_LO) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value
is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.
Refer to
Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.
Note: Both this register and the 1588 Clock Target Low-DWORD Register
(1588_CLOCK_TARGET_LO) must be written for either to be affected.
Offset: 17Ch Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:0 Clock Target High (CLOCK_TARGET_HI)
This field contains the high 32-bits of the 64-bit 1588 Clock Compare value. R/W 00000000h