2 128-xvtqfp pin diagram, Xvtqfp pin diagram, Top view – SMSC LAN9312 User Manual
Page 27
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
27
Revision 1.4 (08-19-08)
DATASHEET
3.1.2
128-XVTQFP Pin Diagram
Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW)
VSS
NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND
SMSC
LAN9312
128-XVTQFP
TOP VIEW
97
VSS
EECLK/EE_SCL/
EEPROM_SIZE_1
EEDO/EEPROM_TYPE
EECS/EEPROM_SIZE_0
VDD33IO
NC
NC
XI
VDD18CORE
VDD18PLL
XO
NC
TEST2
TXP1
TXN1
VSS
VSS
RXN1
VDD33A1
VDD33A1
RXP1
EXRES
VDD18TX1
VDD18TX2
VDD33BIAS
RXP2
VDD33A2
VDD33A2
RXN2
TXN2
TXP2
VSS
VDD33IO
PME
IRQ
FIFO_SEL
END_SEL
nWR
nCS
NC
nRD
VDD33IO
A2
A4
A3
A6
A5
VSS
A7
VDD33IO
A8
D0
A9
D2
D1
VDD18CORE
D3
D4
VDD33IO
D6
D5
D8
D7
VDD33IO
EE
D
I/EE_SD
A
NC
NC
nP
1L
ED
0/
GPI
O
0
VD
D
33I
O
nP
1L
ED
2/
GPI
O
2
nP
1L
ED
1/
GPI
O
1
VD
D
18C
OR
E
nP
1L
ED
3/
GPI
O
3
nP
2L
ED
0/
GPI
O
4
VD
D
33I
O
nP
2L
ED
2/
GPI
O
6
nP
2L
ED
1/
GPI
O
5
GPI
O
8
nP
2L
ED
3/
GPI
O
7
VS
S
VD
D
33I
O
GPI
O
10
GPI
O
9
NC
GPI
O
11
VD
D
18C
OR
E
TEST
1
VD
D
33I
O
VD
D
33I
O
AU
TO
_M
D
IX
_2
nR
ST
PH
Y_
A
D
D
R
_S
EL
AU
TO
_M
D
IX
_1
VD
D
33I
O
LE
D
_E
N
VD
D
18C
OR
E
NC
VD
D
18C
OR
E
NC
D3
0
D3
1
VD
D
33I
O
D2
9
D2
7
D2
8
D2
5
D2
6
VD
D
33I
O
D2
4
D2
3
VD
D
18C
OR
E
D2
1
D2
2
D2
0
VS
S
VD
D
33I
O
D1
9
D1
7
D1
8
D1
5
D1
6
VD
D
33I
O
D1
4
D1
2
D1
3
D1
0
D1
1
D9
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32