8 virtual phy, Datasheet 14.2.8 virtual phy – SMSC LAN9312 User Manual

Page 245

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Datasheet

SMSC LAN9312

245

Revision 1.4 (08-19-08)

DATASHEET

14.2.8

Virtual PHY

This section details the Virtual PHY System CSR’s. These registers provide status and control
information similar to that of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY
registers are addressable via the memory map, as described in

Table 14.1

, as well as serially via the

MII management protocol (IEEE 802.3 clause 22). When accessed serially, these registers are
accessed indirectly through the

Host MAC MII Access Register (HMAC_MII_ACC)

and

Host MAC MII

Data Register (HMAC_MII_DATA)

via the MII serial management protocol specified in IEEE 802.3

clause 22. When being accessed serially, the Virtual PHY will respond when the PHY address equals
the address assigned by the phy_addr_sel_strap configuration strap, as defined in

Section 7.1.1, "PHY

Addressing," on page 82

. A list of all Virtual PHY register indexes for serial access can be seen in

Table 14.4

. For more information on the Virtual PHY access modes, refer to section

Section 14.4

. For

Virtual PHY functionality and operation information, see

Section 7.3, "Virtual PHY," on page 96

Note:

All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management
register set. All functionality and bit definitions comply with these standards. The IEEE 802.3
specified register index (in decimal) is included under the LAN9312 memory mapped offset of
each Virtual PHY register as a reference. For additional information, refer to the IEEE 802.3
Specification.

Note:

When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
management of PHY’s.

Table 14.4 Virtual PHY MII Serially Adressable Register Index

INDEX #

SYMBOL

REGISTER NAME

VPHY_BASIC_CTRL

Virtual PHY Basic Control Register,

Section 14.2.8.1

VPHY_BASIC_STATUS

Virtual PHY Basic Status Register,

Section 14.2.8.2