SMSC LAN9312 - Manual (Page 53)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 53 Revision 1.4 (08-19-08)
DATASHEET
„ TX Status FIFO Overflow
„ Receive Watchdog Time-Out
„ Receiver Error
„ Transmitter Error
„ TX Data FIFO Underrun
„ TX Data FIFO Overrun
„ TX Data FIFO Available
„ TX Status FIFO Full
„ TX Status FIFO Level
„ RX Dropped Frame
„ RX Data FIFO Level
„ RX Status FIFO Full
„ RX Status FIFO Level
In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC
interrupt event must be enabled in the
Interrupt Enable Register (INT_EN) , and IRQ output must be
enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG) .
Refer to the Interrupt Status Register (INT_STS) on page 174 and Chapter 9, "Host MAC," on page 112
for additional information on bit definitions and Host MAC operation.
5.2.6 Power Management Interrupts
Multiple Power Management Event interrupt sources are provided by the LAN9312. The top-level
PME_INT (bit 17) of the
Interrupt Status Register (INT_STS) provides indication that a Power
Management interrupt event occurred in the Power Management Control Register (PMT_CTRL) .
The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all
Power Management conditions. These include energy-detect on the Port 1/2 PHYs, and Wake-On-LAN
(wake-up frame or magic packet) detection by the Host MAC.
In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired
Power Management interrupt event must be enabled in the
Power Management Control Register
(PMT_CTRL) (bits 15, 14, and/or 9), bit 17 (PME_INT_EN) of the Interrupt Enable Register (INT_EN)
must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register
(IRQ_CFG) .
For additional details on power management, refer to Section 4.3, "Power Management," on page 46 .
5.2.7 General Purpose Timer Interrupt
A General Purpose Timer (GPT) interrupt is provided in the top-level Interrupt Status Register
(INT_STS) and Interrupt Enable Register (INT_EN) (bit 19). This interrupt is issued when the General
Purpose Timer Configuration Register (GPT_CFG) wraps past zero to FFFFh, and is cleared when bit
19 of the Interrupt Status Register (INT_STS) is written with 1.
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the bit 29 (TIMER_EN) in the
General Purpose Timer Configuration Register
(GPT_CFG) , bit 19 of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be
enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG) .
For additional details on the General Purpose Timer, refer to Section 12.1, "General Purpose Timer,"
on page 161 .