SMSC LAN9312 - Manual (Page 85)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 85 Revision 1.4 (08-19-08)
DATASHEET
Table 7.2 4B/5B Code Table
CODE
GROUP SYM
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
11110 0 0 0000 DATA 0 0000 DATA
01001 1 1 0001 1 0001
10100 2 2 0010 2 0010
10101 3 3 0011 3 0011
01010 4 4 0100 4 0100
01011 5 5 0101 5 0101
01110 6 6 0110 6 0110
01111 7 7 0111 7 0111
10010 8 8 1000 8 1000
10011 9 9 1001 9 1001
10110 A A 1010 A 1010
10111 B B 1011 B 1011
11010 C C 1100 C 1100
11011 D D 1101 D 1101
11100 E E 1110 E 1110
11101 F F 1111 F 1111
11111 /I/ IDLE Sent after /T/R/ until the MII Transmitter
Enable signal (TXEN) is received
11000 /J/ First nibble of SSD, translated to “0101”
following IDLE, else MII Receive Error
(RXER) Sent for rising MII Transmitter Enable
signal (TXEN)
10001 /K/ Second nibble of SSD, translated to
“0101” following J, else MII Receive
Error (RXER) Sent for rising MII Transmitter Enable
signal (TXEN)
01101 /T/ First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of MII Receive Error (RXER) Sent for falling MII Transmitter Enable
signal (TXEN)
00111 /R/ Second nibble of ESD, causes de-
assertion of CRS if following /T/, else
assertion of MII Receive Error (RXER) Sent for falling MII Transmitter Enable
signal (TXEN)
00100 /H/ Transmit Error Symbol Sent for rising MII Transmit Error (TXER)
00110 /V/ INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV) INVALID
11001 /V/ INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV) INVALID
00000 /V/ INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV) INVALID
00001 /V/ INVALID, MII Receive Error (RXER) if
during MII Receive Data Valid (RXDV) INVALID