SMSC LAN9312 - Manual (Page 187)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 187 Revision 1.4 (08-19-08)
DATASHEET
14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)
This read-write register is used to control the read and write operations to/from the Host MAC. This
register in used in conjunction with the
Host MAC CSR Interface Data Register (MAC_CSR_DATA) to
indirectly access the Host MAC CSR’s.
Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status
Registers," on page 269 . For more information on the Host MAC, refer to Chapter 9, "Host
MAC," on page 112 .
Offset: 0A4h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31 CSR Busy
When a 1 is written into this bit, the read or write operation is performed to
the specified Host MAC CSR. This bit will remain set until the operation is
complete. In the case of a read, this indicates that the host can read valid
data from the
Host MAC CSR Interface Data Register (MAC_CSR_DATA) .
Note: The MAC_CSR_CMD and MAC_CSR_DATA registers must not be
modified until this bit is cleared.
R/W
SC
0b
30 R/nW
When set, this bit indicates that the host is requesting a read operation.
When clear, the host is performing a write.
0: Host MAC CSR Write Operation
1: Host MAC CSR Read Operation
R/W 0b
29:8 RESERVED RO -
7:0 CSR Address
The 8-bit value in this field selects which Host MAC CSR will be accessed
by the read or write operation. The index of each Host MAC CSR is defined
in
Section 14.3, "Host MAC Control and Status Registers," on page 269 .
R/W 00h