3 virtual phy pause flow control, 2 virtual phy resets, 1 virtual phy software reset via reset_ctl – SMSC LAN9312 User Manual

Page 98: 2 virtual phy software reset via vphy_basic_ctrl, 3 virtual phy software reset via pmt_ctrl, Virtual phy pause flow control, Virtual phy resets, Virtual phy software reset via reset_ctl, Virtual phy software reset via vphy_basic_ctrl, Virtual phy software reset via pmt_ctrl

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

SMSC LAN9312

DATASHEET

7.3.1.3

Virtual PHY Pause Flow Control

The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs
advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric
Pause) of the

Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)

. This allows the

Virtual PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the
emulated link partner. The default values of these bits are as shown in

Section 14.2.8.5, "Virtual PHY

Auto-Negotiation Advertisement Register (VPHY_AN_ADV)," on page 252

The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY in (bits 10 & 11) of the

Virtual PHY Auto-Negotiation

Advertisement Register (VPHY_AN_ADV)

. Thus, the emulated link partner always accommodates the

asymmetric/symmetric pause ability settings requested by the Virtual PHY, as shown in

Table 14.5,

“Emulated Link Partner Pause Flow Control Ability Default Values,” on page 255

The pause flow control settings may also be manually set via the

Port 0(Host MAC) Manual Flow

Control Register (MANUAL_FC_MII)

. This register allows the switch fabric port 0 flow control settings

to be manually set when auto-negotiation is disabled or the Manual Flow Control Select bit 0 is set.
The currently enabled duplex and flow control settings can also be monitored via this register. The flow
control values in the

Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)

are not

affected by the values of the manual flow control register. Refer to

Section 6.2.3, "Flow Control Enable

Logic," on page 58

for additional information.

7.3.2

Virtual PHY Resets

In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports three block specific resets. These are is discussed in the following sections. For detailed
information on all LAN9312 resets, refer to

Section 4.2, "Resets," on page 36

7.3.2.1

Virtual PHY Software Reset via RESET_CTL

The Virtual PHY can be reset via the

Reset Control Register (RESET_CTL)

by setting bit 3

(VPHY_RST). This bit is self clearing after approximately 102uS.

7.3.2.2

Virtual PHY Software Reset via VPHY_BASIC_CTRL

The Virtual PHY can also be reset by setting bit 15 (VPHY_RST) of the

Virtual PHY Basic Control

. This bit is self clearing and will return to 0 after the reset is complete.