SMSC LAN9312 - Manual (Page 217)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 217 Revision 1.4 (08-19-08)
DATASHEET
14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)
T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h 1 5 8 8 C l o c k Ta r g e t H i g h - D W O R D R e g i s t e r
(1588_CLOCK_TARGET_HI) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is
compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer
to
Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.
Note: Both this register and the 1588 Clock Target High-DWORD Register
(1588_CLOCK_TARGET_HI) must be written for either to be affected.
Offset: 180h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:0 Clock Target Low (CLOCK_TARGET_LO)
This field contains the low 32-bits of the 64-bit 1588 Clock Compare value. R/W 00000000h