SMSC LAN9312 - Manual (Page 394)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 394 SMSC LAN9312
DATASHEET
14.5.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
This register is used to indirectly read and write the ingress rate metering/color table registers. A write
to this address performs the specified access.
For a read access, the Operation Pending bit in the Switch Engine Ingress Rate Command Status
Register (SWE_INGRSS_RATE_CMD_STS) indicates when the command is finished. The Switch
Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) can then be read.
F o r a w r i t e a c c e s s , t h e S w i t c h E n g i n e I n g r e s s R a t e W r i t e D a t a R e g i s t e r
(SWE_INGRSS_RATE_WR_DATA) should be written first. The Operation Pending bit in the Switch
Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) indicates when the
command is finished.
For details on 16-bit wide Ingress Rate Table registers indirectly accessible by this register, see
Section 14.5.3.26.1 below.
Register #: 184Bh Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:8 RESERVED RO -
7 Ingress Rate RnW
These bits specify a read(1) or write(0) command. R/W 0b
6:5 Type
These bits select between the ingress rate metering/color table registers as
follows:
00 = RESERVED
01 = Committed Information Rate Registers
(uses CIS Address field)
10 = Committed Burst Register
11 = Excess Burst Register
R/W 00b
4:0 CIR Address
These bits select one of the 24 Committed Information Rate registers.
When Rate Mode is set to Source Port & Priority in the Switch Engine
Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) , the first
set of 8 registers (CIR addresses 0-7) are for to Port 0, the second set of 8
registers (CIR addresses 8-15) are for Port 1, and the third set of registers
(CIR addresses 16-23) are for Port 2. Priority 0 is the lower register of each
set (e.g. 0, 8, and 16).
When Rate Mode is set to Source Port Only, the first register (CIR address
0) is for Port 0, the second register (CIR address 1) is for Port 1, and the
third register (CIR address 2) is for Port 2.
When Rate Mode is set to Priority Only, the first register (CIR address 0) is
for priority 0, the second register (CIR address 1) is for priority 1, and so
forth up to priority 23.
Note: Values outside of the valid range may cause unexpected results.
R/W 0h