SMSC LAN9312 - Manual (Page 285)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 285 Revision 1.4 (08-19-08)
DATASHEET
14.4 Ethernet PHY Control and Status Registers
This section details the various LAN9312 Ethernet PHY control and status registers. The LAN9312
contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE
802.3 (clause 22.2.4) specified MII management register set. All functionality and bit definitions comply
with these standards. The IEEE 802.3 specified register index (in decimal) is included with each
register definition, allowing for addressing of these registers via the MII serial management protocol.
For additional information on the MII management protocol, refer to the IEEE 802.3 Specification.
Each individual PHY is assigned a unique PHY address as detailed in Section 7.1.1, "PHY
Addressing," on page 82 .
14.4.1 Virtual PHY Registers
The Virtual PHY provides a basic MII management interface for communication with the Host MAC for
connection to the Host as if it was attached to a single port PHY. The Virtual PHY registers differ from
the Port 1 & 2 PHY registers in that they are addressable via the memory map, as described in
Table 14.1 , as well as serially. These modes of access are described in Section 14.2.8, "Virtual PHY,"
on page 245 .
Because the Virtual PHY registers are also memory mapped, their definitions have been included in
the
System Control and Status Registers Section 14.2.8, "Virtual PHY," on page 245 . A list of the Virtual
PHY MII addressable registers and their corresponding register index numbers is also included in
Table 14.4 .
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
management of PHY’s.
14.4.2 Port 1 & 2 PHY Registers
The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory
mapped registers. The Port 1 and Port 2 PHY registers are not memory mapped. These registers are
indirectly accessed through the
Host MAC MII Access Register (HMAC_MII_ACC) and Host MAC MII
Data Register (HMAC_MII_DATA) registers in the Host MAC via the MII serial management protocol
specified in IEEE 802.3 clause 22. Because the Port 1 & 2 PHY registers are functionally identical,
their register descriptions have been consolidated. A lowercase “x” has been appended to the end of
each PHY register name in this section, where “x” should be replaced with “1” or “2” for the Port 1
PHY or the Port 2 PHY registers respectively. A list of the Port 1 & 2 PHY MII addressable registers
and their corresponding register index numbers is included in
Table 14.7 . Each individual PHY is
assigned a unique PHY address as detailed in Section 7.1.1, "PHY Addressing," on page 82 .
Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers
INDEX # SYMBOL REGISTER NAME
0 PHY_BASIC_CONTROL_x Port x PHY Basic Control Register, Section 14.4.2.1
1 PHY_BASIC_STATUS_x Port x PHY Basic Status Register, Section 14.4.2.2
2 PHY_ID_MSB_x Port x PHY Identification MSB Register, Section 14.4.2.3
3 PHY_ID_LSB_x Port x PHY Identification LSB Register, Section 14.4.2.4
4 PHY_AN_ADV_x Port x PHY Auto-Negotiation Advertisement Register,
Section 14.4.2.5
5 PHY_AN_LP_BASE_ABILITY_x Port x PHY Auto-Negotiation Link Partner Base Page Ability
Register,
Section 14.4.2.6
6 PHY_AN_EXP_x Port x PHY Auto-Negotiation Expansion Register,
Section 14.4.2.7