SMSC LAN9312 - Manual (Page 128)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 128 SMSC LAN9312
DATASHEET
9.8.5 Calculating Actual TX Data FIFO Usage
The following rules are used to calculate the actual TX Data FIFO space consumed by a TX Packet:
„ TX command 'A' is stored in the TX Data FIFO for every TX buffer
„ TX command 'B' is written into the TX Data FIFO when the First Segment (FS) bit is set in TX
command 'A'
„ Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before
the data is written to the TX Data FIFO. Any data that is less than 1 DWORD is passed to the TX
Data FIFO.
„ Payload from each buffer within a Packet is written into the TX Data FIFO.
„ Any DWORD-long data added as part of the End Padding is removed from each buffer before the
data is written to the TX Data FIFO. Any end padding that is less than 1 DWORD is passed to the
TX Data FIFO
9.8.6 Transmit Examples
9.8.6.1 TX Example 1
In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three
buffers. The three buffers are as follows:
Buffer 0:
„ 7-Byte “Data Start Offset”
„ 79-Bytes of payload data
„ 16-Byte “Buffer End Alignment”
Buffer 1:
„ 0-Byte “Data Start Offset”
„ 15-Bytes of payload data
„ 16-Byte “Buffer End Alignment”
Buffer 2:
„ 10-Byte “Data Start Offset”
„ 17-Bytes of payload data
9 Late Collision. When set, indicates that the packet transmission was aborted after the collision
window of 64 bytes.
8 Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16
collisions while attempting to transmit the current packet.
7 Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
6:3 Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
2 Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
1 Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility
0 Deferred. When set, this bit indicates that the current packet transmission was deferred.
BITS DESCRIPTION