SMSC LAN9312 - Manual (Page 321)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 321 Revision 1.4 (08-19-08)
DATASHEET
14.5.1.4 Switch Global Interrupt Pending Register (SW_IPR)
This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates
an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related
interrupts in this register may be masked via the
Switch Global Interrupt Mask Register (SW_IMR)
register. When an unmasked switch fabric interrupt is generated in this register, the interrupt will trigger
the SWITCH_INT bit in the
Interrupt Status Register (INT_STS) . Refer to Chapter 5, "System
Interrupts," on page 49 for more information.
Register #: 0005h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:7 RESERVED RO -
6 Buffer Manager Interrupt (BM)
Set when any unmasked bit in the
Buffer Manager Interrupt Pending
Register (BM_IPR) is triggered. This bit is cleared upon a read.
RC 0b
5 Switch Engine Interrupt (SWE)
Set when any unmasked bit in the
Switch Engine Interrupt Pending Register
(SWE_IPR) is triggered. This bit is cleared upon a read.
RC 0b
4:3 RESERVED RO -
2 Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see
Section
14.5.2.44, on page 365 ) is triggered. This bit is cleared upon a read.
RC 0b
1 Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see
Section
14.5.2.44, on page 365 ) is triggered. This bit is cleared upon a read.
RC 0b
0 Port 0 MAC Interrupt (MAC_MII)
Set when any unmasked bit in the MAC_IPR_MII register (see
Section
14.5.2.44, on page 365 ) is triggered. This bit is cleared upon a read.
RC 0b