5 pio burst read cycle timing, Figure 15.5 pio burst read cycle timing, Table 15.9 pio burst read cycle timing values – SMSC LAN9312 User Manual
Page 447: Datasheet 15.5.5 pio burst read cycle timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
447
Revision 1.4 (08-19-08)
DATASHEET
15.5.5
PIO Burst Read Cycle Timing
Please refer to
Section 8.4.5, "PIO Burst Reads," on page 107
for a functional description of this mode.
Note:
A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
Note:
Fresh data is supplied each time A[2] toggles.
Figure 15.5 PIO Burst Read Cycle Timing
Table 15.9 PIO Burst Read Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
csh
nCS, nRD De-assertion Time
13
nS
t
csdv
nCS, nRD Valid to Data Valid
30
nS
t
acyc
Address Cycle Time
45
nS
t
asu
Address Setup to nCS, nRD Valid
0
nS
t
adv
Address Stable to Data Valid
40
nS
t
ah
Address Hold Time
0
nS
t
don
Data Buffer Turn On Time
0
nS
t
doff
Data Buffer Turn Off Time
9
nS
t
doh
Data Output Hold Time
0
nS
A[4:2]
nCS, nRD
D[31:0]
A[x:5], END_SEL
t
asu
t
acyc
t
acyc
t
acyc
t
ah
t
csh
t
adv
t
adv
t
adv
t
csdv
t
don
t
doh
t
doff