SMSC LAN9312 - Manual (Page 110)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 110 SMSC LAN9312
DATASHEET
8.4.8 PIO Writes
PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle
ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must
de-assert between cycles for the period specified in
Table 15.12, “PIO Write Cycle Timing Values,” on
page 450 . They may be asserted and de-asserted in any order. Either or both of these control signals
must be de-asserted between cycles for the period specified. The PIO write cycle is illustrated in the
functional timing diagram in
Figure 8.7 .
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to Section 15.5.8, "PIO Write Cycle Timing," on page 450 for the AC timing specifications
for PIO write operations.
Figure 8.7 Functional Timing for PIO Write Operation
VALID
VALID D[31:0] (INPUT)
nCS, nWR
A[x:2]
VALID END_SEL