SMSC LAN9312 - Manual (Page 159)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312 159 Revision 1.4 (08-19-08)
DATASHEET
11.3 IEEE 1588 Clock
The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9312. It
is readable and writable by the host via the
1588 Clock High-DWORD Register (1588_CLOCK_HI) and
1588 Clock Low-DWORD Register (1588_CLOCK_LO) .
In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads
are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a
wrong intermediate value could be read. To prevent this, a snapshot register technique is used. When
the 1588_CLOCK_SNAPSHOT bit in the
1588 Command Register (1588_CMD) register is written with
“1”, the current value of the 1588 clock is saved, allowing it to be properly read.
When writing a new value to the IEEE 1588 clock, two 32-bit write cycles are required (one for each
clock register) before the registers are affected. The writes may be in any order. However, caution must
be observed when changing the clock value in a live environment as it will disrupt linear time. If the
clock must be adjusted during operation of the 1588 protocol, it is preferred to adjust the Addend value,
effectively speeding-up or slowing-down the clock until the correct time is achieved.
T h e 6 4 - b i t I E E E 1 5 8 8 c l o c k c o n s i s t s o f t h e 3 2 - b i t 1 5 8 8 C l o c k A d d e n d R e g i s t e r
(1588_CLOCK_ADDEND) that is added to a 32-bit Accumulator every 100 MHz clock. Upon overflow
of the Accumulator, the 64- bit IEEE 1588 clock is incremented. The Addend / Accumulator pair form
a high precision frequency divider which can be used to compensate for the inaccuracy of the
reference crystal. The nominal frequency of the 64-bit IEEE 1588 clock and the value of the Addend
are calculated as follows:
FreqClock = (Addend / 2
32
) * 100 MHz
Addend = (FreqClock * 2 32 ) / 100 MHz
Typical values for the Addend are shown in Table 11.4 . These values should be adjusted based on the
accuracy of the IEEE 1588 clock compared to the master clock per the PTP protocol. The adjustment
precision column of the table shows the percentage change for the specified IEEE 1588 clock
frequency if the Addend was to be incremented or decremented by 1.
Table 11.4 Typical IEEE 1588 Clock Addend Values
IEEE 1588 CLOCK
(FreqClock)
1588_CLOCK_ADDEND
(Addend) ADJUSTMENT PRECISION %
33 MHz 547AE147h 7.1*10 -8
50 MHz 80000000h 4.7*10
-8
66 MHz A8F5C28Fh 3.5*10
-8
75 MHz C0000000h 3.1*10 -8
90 MHz E6666666h 2.6*10
-8