9 tx data fifo direct pio write cycle timing – SMSC LAN9312 User Manual
Page 451
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
451
Revision 1.4 (08-19-08)
DATASHEET
15.5.9
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to
Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111
description of this mode.
Note:
A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
cycle
Write Cycle Time
45
nS
t
csl
nCS, nWER Assertion Time
32
nS
t
csh
nCS, nWR De-assertion Time
13
nS
t
asu
Address, FIFO_SEL Setup to nCS, nWR Assertion
0
nS
t
ah
Address, FIFO_SEL Hold Time
0
nS
t
dsu
Data Setup to nCS, nWR De-assertion
7
nS
t
dh
Data Hold Time
0
nS
t
ah
t
dsu
A[2], END_SEL
nCS, nWR
D[31:0]
FIFO_SEL
t
dh
t
csh
t
cycle
t
csl
t
asu