SMSC LAN9312 - Manual (Page 364)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 364 SMSC LAN9312
DATASHEET
14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x)
This register contains the Port x interrupt mask. Port x related interrupts in the Port x MAC Interrupt
Pending Register (MAC_IPR_x) may be masked via this register. An interrupt is masked by setting the
corresponding bit of this register. Clearing a bit will unmask the interrupt. Refer to Chapter 5, "System
Interrupts," on page 49 for more information.
Note: There are no possible Port x interrupt conditions available. This register exists for future use,
and should be configured as indicated for future compatibility.
Register #: Port0: 0480h Size: 32 bits
Port1: 0880h
Port2: 0C80h
BITS DESCRIPTION TYPE DEFAULT
31:8 RESERVED RO -
7:0 RESERVED
Note: These bits must be written as 11h
R/W 11h