Chapter 7 ethernet phys, 1 functional overview, 1 phy addressing – SMSC LAN9312 User Manual

Page 82: Table 7.1 default phy serial mii addressing, Chapter 7, Ethernet phys, Functional overview, Phy addressing, Section, Datasheet

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

82

SMSC LAN9312

DATASHEET

Chapter 7 Ethernet PHYs

7.1

Functional Overview

The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs
are identical in functionality and each connect their corresponding Ethernet signal pins to the switch
fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII
interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of the Host
MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with
the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100
Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow the IEEE
802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly via the
Host MAC, or directly via the memory mapped Virtual PHY registers. Refer to

Section 14.4, "Ethernet

PHY Control and Status Registers"

for details on the Ethernet PHY registers.

The LAN9312 Ethernet PHYs are discussed in detail in the following sections:

„

Section 7.2, "Port 1 & 2 PHYs," on page 83

„

Section 7.3, "Virtual PHY," on page 96

7.1.1

PHY Addressing

Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap
configuration strap as shown in

Table 7.1

. In addition, the Port 1 PHY and Port 2 PHY addresses can

be changed via the

PHY Address (PHYADD)

field in the

Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x)

. For proper operation, all LAN9312 PHY addresses must be unique. No

check is performed to assure each PHY is set to a different address. Configuration strap values are
latched upon the de-assertion of a chip-level reset as described in

Section 4.2.4, "Configuration

Straps," on page 40

.

Table 7.1 Default PHY Serial MII Addressing

PHY_ADDR_SEL_STRAP

VIRTUAL PHY DEFAULT

ADDRESS VALUE

PORT 1 PHY DEFAULT

ADDRESS VALUE

PORT 2 PHY DEFAULT

ADDRESS VALUE

0

0

1

2

1

1

2

3

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