SMSC LAN9312 - Manual (Page 21)

High Perfo
rmance T
w
o Por
t 10/10
0
Managed Etherne
t
Switch
with 32-
Bit Non
-PC
I
CPU Inte
rfac
e
Dat
ashe
e
t
Revision 1.4 (0
8-19-
08)
21
S
M
SC
LAN9312
DA
T
ASHEET
2.2 Block Diagram
Figure 2.1 Internal LAN9312 Block Diagram
To optional
EEPROM
EEPROM Controller
I 2 C (master)
Microwire (master)
EEPROM Loader
Register
Access
MUX
System
Registers
(CSRs)
I 2 C/Microwire
MII
IEEE 1588
Time Stamp
Registers
Virtual PHY
10/100
PHY
Registers
10/100
PHY
Registers
Switch
Registers
(CSRs)
IEEE 1588
Time Stamp
IEEE 1588
Time Stamp
Switch Fabric
GPIO/LED
Controller
D
y
nam
ic
Qo
S
4 Q
u
eu
e
s
Dyn
a
m
ic
Qo
S
4 Q
u
e
u
es
D
y
nam
ic
Qo
S
4 Q
u
eu
e
s
Switch Engine
Buffer Manager
Search
Engine
Frame
Buffers
IEEE 1588
Time Stamp
Clock/Events
MII
MDIO
MII
MDIO
To optional GPIOs/LEDs
To Ethernet
To Ethernet
LAN9312
Host Bus Interface
TX/RX FIFOs
Host MAC
To 32-bit
Host Bus
System
Interrupt
Controller
IRQ
GP Timer
Free-Run
Clk
System
Clocks/
Reset/PME
Controller
External
25MHz Crystal
MD
IO
MD
IO
MDIO
Po
rt 0
10/100
MAC
Po
rt 2
10/100
MAC
Po
rt 1
10/100
MAC