4 pio read cycle timing, Figure 15.4 pio read cycle timing, Table 15.8 pio read cycle timing values – SMSC LAN9312 User Manual
Page 446: Datasheet 15.5.4 pio read cycle timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
446
SMSC LAN9312
DATASHEET
15.5.4
PIO Read Cycle Timing
Please refer to
Section 8.4.4, "PIO Reads," on page 106
for a functional description of this mode.
Note:
A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted
in any order.
Figure 15.4 PIO Read Cycle Timing
Table 15.8 PIO Read Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
cycle
Read Cycle Time
45
nS
t
csl
nCS, nRD Assertion Time
32
nS
t
csh
nCS, nRD De-assertion Time
13
nS
t
csdv
nCS, nRD Valid to Data Valid
30
nS
t
asu
Address setup to nCS, nRD Valid
0
nS
t
ah
Address Hold Time
0
nS
t
don
Data Buffer Turn On Time
0
nS
t
doff
Data Buffer Turn Off Time
9
nS
t
doh
Data Output Hold Time
0
nS
t
ah
A[x:2], END_SEL
nCS, nRD
D[31:0]
t
asu
t
cycle
t
csh
t
csl
t
csdv
t
don
t
doh
t
doff