Samsung S3F401F - Manual (Page 125)

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER
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INTERRUPT CONTROLLER
1. OVERVIEW
Even if there are many interrupt request sources, the ARM7TDMI-S core can only recognize all interrupt as two
kinds of interrupt: IRQ (a normal Interrupt Request) and FIQ(a Fast Interrupt Request). Therefore, all interrupt
sources in S3F401F should be categorized as either IRQ or FIQ. The multiple interrupt sources should be
controlled by three kind of information in special registers in interrupt controller. These are INTMOD, INTPND, and
INTMSK register. The role of three registers in interrupt controller is as follow.
In S3F401F, the interrupt controller can support the interrupt vector base address as well as programmable
priority. To reduce the interrupt latency, the interrupt controller in S3F401F assigned the hard-wired vector
address according to each interrupt source for hard-wired base address branch, and also has the interrupt offset
register, INTOFFS which contains the interrupt offset address of the interrupt source for software base address
branch.
The total 90’s interrupt request sources to CPU can have the programmable priority. This feature of
programmable priority can make you to have more intelligent interrupt handling.
• INTMOD - Interrupt Mode Register: Defines the interrupt mode for each interrupt source, which is IRQ or
FIQ. By having the configuration for each interrupt source in this register, you can allocate all interrupt sources
as IRQ or FIQ mode interrupt.
• INTPND - Interrupt Pending Register: In CPU core, there is PSR (Processor Status Register) register, which
has several fields including I-Flag and F-Flag relating the interrupt. As mentioned above, the CPU can accept
two kinds of interrupt even if S3F401F has the total 90-interrupt sources. That is why all interrupt sources in
S3F401F should be categorized into two modes, which is IRQ mode and FIQ mode. In this case, if CPU is
running the service for a certain interrupt, and if the mode of interrupt is IRQ mode, the other interrupt sources
with IRQ mode can not be serviced until the current service is completed. These interrupts should be pending
in INTPND (Interrupt Pending Register). In case of FIQ mode, other FIQ interrupt request can not take CPU
while the current FIQ service is running as same as IRQ case. Therefore, the FIQ interrupt request should be
pending in INTPND as same as IRQ. If IRQ interrupt service is running, the FIQ interrupt can take the CPU for
service because FIQ has higher priority than IRQ in hardware. In other word, ARM CPU can support two levels
interrupt architecture. The pending interrupt service can start whenever the I-Flag or F-Flag should be cleared
to ‘0. The service routine should clear the pending bit, also.'
• INTMSK - Interrupt Mask Register: If this mask bit is set, the corresponding interrupt request should be
enabled. You can select the interrupt enable or disable by using this register. For masking (Disable the
interrupt), the corresponding mask bit should be ‘0’.
• INTOFFS - Interrupt Offset Register: This have the interrupt offset address of the interrupt source which has
the highest priority according to the interrupt priority setting among the pending interrupts, when interrupts
occur.