Samsung S3F401F - Manual (Page 249)

S3F401F_UM_REV1.00 UART
12-11
3.7.3 IrDA SIR Receive Decoder
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the
received NRZ serial bit stream to the UART received data input. The decoder input is normally HIGH (marking
state) in the idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is
detected when the decoder input is LOW. Regardless of being in normal or low-power mode, a start bit is deemed
valid if the decoder is still LOW, one period of IrLPBaud16 after the LOW was first detected. This enables a
normal-mode UART to receive data from a low-power mode UART, that can transmit pulses as small as 1.41µs.
3.8 INTERRUPTS
Interrupt Description
UARTRXINTR Receive Interrupt
UARTTXINTR Transmit Interrupt
UARTOEINTR Error Interrupt: Overrun detection
UARTBEINTR Error Interrupt: Break in the reception
UARTPEINTR Error Interrupt: Parity error in the received character
UARTEINTR
UARTFEINTR Error Interrupt: Framing error in the received character
You can enable or disable the individual interrupts by changing the mask bits in the UARTIMSC register.
Setting the appropriate mask bit HIGH enables the interrupt. Provision of individual outputs as well as a combined
interrupt output, enables you to use either a global interrupt service routine, or modular device drivers to handle
interrupts.
The transmit and receive dataflow interrupts, UARTRXINTR and UARTTXINTR, have been separated from the
status interrupts. This enables you to use UARTRXINTR and UARTTXINTR so that data can be read or written in
response to the FIFO trigger levels.
The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of data. A number of
error conditions are possible.
The status of the individual interrupt sources can be read either from UARTRIS, for raw interrupt status, or from
the UARTMIS, for the masked interrupt status.