Samsung S3F401F - Manual (Page 209)

SSP S3F401F_UM_REV1.00
10-8
In the case of a single word transmission, after all bits of the data word have been transferred, the SSPFSS line is
returned to its idle HIGH state one SSPCLK period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSS signal must be pulsed HIGH between
each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and
does not allow it to be altered if the SPH bit is logic zero. Therefore the master device must raise the SSPFSS pin of
the slave device between each data transfer to enable the serial peripheral data write. On completion of the
continuous transfer, the SSPFSS pin is returned to its idle state one SSPCLK period after the last bit has been
captured.
2.2.2 SSP format with SPO=0, SPH=1
The transfer signal sequence for Motorola SPI format with SPO=0, SPH=1 is shown in below figure, which covers
both single and continuous transfers.
4 to 16 bits
SSPCLK
SSPFSS
SSPRXD Q LSB MSB
LSB MSB
SSPTXD
Q
Figure 10-5. SSP frame format with SPO=0 and SPH=1
In this configuration, during idle periods:
• The SSPCLK signal is forced LOW
• SSPFSS is forced HIGH
• The transmit data line SSPTXD is arbitrarily forced LOW
• When the SSP is configured as a master, the SSPCLK is enabled.
• When the SSP is configured as a slave the SSPCLK is disabled.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSS master signal being driven LOW. The master SSPTXD output pad is enabled. After a further one half
SSPCLK period, both master and slave valid data is enabled onto their respective transmission lines. At the same
time, the SSPCLK is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSPCLK signal.
In the case of a single word transfer, after all bits have been transferred, the SSPFSS line is returned to its idle HIGH
state one SSPCLK period after the last bit has been captured.
For continuous back-to-back transfers, the SSPFSS pin is held LOW between successive data words and
termination is the same as that of the single word transfer.