Samsung S3F401F - Manual (Page 144)

INTERRUPT CONTROLLER S3F401F_UM_REV1.00
7-20
INTERRUPT VECTOR ADDRESS Register for IRQ INTIRQADDR (0x028) Access: Read Only
31 30 29 28 27 26 25 24
INTIRQADDR [31:24]
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23 22 21 20 19 18 17 16
INTIRQADDR [23:16]
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8
INTIRQADDR [15:8]
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
INTIRQADDR [7:0]
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
Each Interrupt Type Selection Bit INTIRQADDR
The value of this register represents the interrupt vector address of FIQ.
Interrupt vector address register for IRQ.
Indicates the interrupt vector address of interrupt IRQ source, which has the highest
priority among the pending interrupts.