Samsung S3F401F - Manual (Page 243)

S3F401F_UM_REV1.00 UART
12-5
2. BLOCK DIAGRAM
Buad-rate
Generator
Control
Unit
Transmit Shifter
Transmit FIFO
Register(16 Byte)
Transmitter
Receive FIFO
Register(16 Byte)
Receive Shifter
Receiver
Peripheral BUS
TXn
PCLK
RXn
Transmit Buffer Register
(Transmit FIFO and
Holding Register)
Transmit Holding Register
(Non-FIFO mode only)
Receive Buffer Register
(Receive FIFO and
Holding Register)
Receive Holding Register
(Non-FIFO mode only)
Figure 12-1. UART Block Diagram (with FIFO)