Samsung S3F401F - Manual (Page 246)

UART S3F401F_UM_REV1.00
12-8
3.6.2 Data Transmission or Reception
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per
character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it
causes a data frame to start transmitting with the parameters indicated in UARTLCR_H. Data continues to be
transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written
to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted.
BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift
register, including the stop bits. BUSY can be asserted HIGH even though the UART might no longer be enabled.
For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs the
middle sampling point is defined, and one sample is taken either side of it.
When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is detected on the data
input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and
data is sampled on the eighth cycle of that counter in normal UART mode, or the fourth cycle of the counter in SIR
mode to allow for the shorter logic 0 pulses (half way through a bit period).
The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected
and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is,
one bit period later) according to the programmed length of the data characters. The parity bit is then checked if
parity mode was enabled.
Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full
word is received, the data is stored in the receive FIFO, with any error bits associated with that word
3.6.3 Error Bits
Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a particular character. There
is an additional error that indicates an overrun error and this is stored in bit 11 of the receive FIFO.
3.6.4 Overrun Bit
The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is
full, and the next character is completely received in the shift register. The data in the shift register is overwritten,
but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character
is received, the state of the overrun bit is copied into the receive FIFO along with the received character. The
overrun state is then cleared.
FIFO bit Function
11 Overrun indicator
10 Break error
9 Parity error
8 Framing error
7:0 Received data